1. Field of Art
The disclosure generally relates to a level shifter with a low voltage loss between a source and sink. More specifically, the disclosure relates to a level shifter with voltage loss between two video interfaces operating at different voltages.
2. Description of the Related Art
In converting from one interface standard to another, the voltage level of signals being transmitted may need to be adjusted. For example, DISPLAYPORT (DP) is capable of emitting single link High-Definition Multimedia Interface (HDMI) signals in dual-mode DP. DP operates at 3.3 volts, while HDMI operates at 5 volts. For compatibility, a level shifter is included between a DP source and an HDMI sink. Conventionally, a 3.3V n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pass gate is used to block 5V signals from the HDMI sink. However, with the gate tied to 3.3V, the maximum voltage output is 3.3V less a threshold voltage. With the threshold voltage possibly reaching near 1 V or higher, the maximum voltage output of the signal after level shifting is significantly reduced. This can produce costly logic errors during reception. In addition, certain configurations do not release the display data channel when power is not provided to the level shifter. This can increase power consumption in situations where level shifting is unnecessary, but a signal must still be transmitted.